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- Objective 1: To fabricate a large scale, two dimensional Silicon Photonics chip with 128 lanes on 100mm2 requiring a density of ~0.8mm2 per channel.
- Objective 2: To integrate 128 hybrid silicon III-V laser sources on 100mm2
- Objective 3: Vertical (3D) chip package for integration of the Silicon Photonic chip on a digital CMOS chip enabling a total bandwidth of 3.2Tb/s in an area of 100mm2 or less
- Objective 4: Vertical fibre coupling of fibre arrays with 128 fibres with a loss less than 3dB per fibre.
- Objective 5: Improvement of the power efficiency to the 3pJ/bit range
- Objective 6: Reduce the port-to-port latency to less than 20ns
- Objective 7: Scalable data centre architecture into the Pb/s scale
- Objective 8: Data centre usage scenario that allows direct fibre-to-ASIC termination of commercial single mode transceivers reducing the cost for DEC equipment with more than 40%.